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IW4013B
Description
The IW4013B consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Qoutput to the data input,for counter and toggle applications. The logic level present at the Q output during the positive- going Input is transferred to the Transition of the clock pulse. Setting or Dresetting is independent of clock and is accomplished by a high level on the set or reset line,respectively. the
Features
Operating Voltage Range: 3.0 to 18 V Maximum input current of 1 u A at 18 V over full packagetemperature range ;100 nA at 18 V and 25 C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
14 1
SOP 14
14 1
DIP
14
Package
Logic Diagram
Set 1
Pin Assignment
Q1
Vcc
6 5 3 1
Q1
Q1
Clock 1 Reset 1
Q2 Q2
Clock 2 Reset 2 Data 2 Set 2
Data 1 Clock 1 Reset 1 Set 2
Data 1 Set 1
2
Q1
GND
4 8 13
Q2
Function Table
Inputs Clock Data Reset Set L H X X X X X X X L L L H L H L L L L H H
Q2
Data 2 Clock 2
9 11 10
Outputs Q L H Q L H H Q H L Q H L H
12
Reset 2
PIN 14 = V DD PIN 7 =
X = don ' t care
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IW4013B
Absolute Maximum Ratings
Symbol VCC VIN IIN PD Ptot Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic SOIC Package Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) DIP, Value -0.5 to +20 -0.5 to V +0.5 CC + 10 500 100 -65 to +150 260 Unit V V mA mW mW C C
Power Dissipation per Output Transistor
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP from - 55 to+100 C C - SOIC Package from -55 to + 65 - Plastic DIP: - 12 mW/ from +100 to+125 C C C - SOIC Package: : - 7 mW/ from +65 to+125 C
Recommended Operating Conditions
Symbol VCC VIN TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation VIN should be constrained to the range GND VIN VCC . Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC ). Unused outputs must be left open.
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IW4013B
DC Electrical Characteristics
VCC Symbol VIH Parameter Test Conditions V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 (Voltages Referenced to GND) Guaranteed Limit -55 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 + 0.1 1 2 4 20 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 + 0.1 1 2 4 20 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 + 1.0 30 60 120 600 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V
Minimum High-Level VOUT=0.5 V or VCC - 0.5 V Input Voltage VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or V - 1.5 V CC Maximum Low Level Input Voltage VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or V - 1.5 V CC
VIL
V
VOH
Minimum High-Level VIN=GND or VCC Output Voltage VIL =1.5V, VIH=3.5V, IO=-1 A VIL =3.0V, VIH=7.0V, IO=-1 A VIL =4.0V, VIH=11V, IO=-1 A
V
VOL
Maximum Low-Level VIN=GND or VCC Output Voltage VIL =1.5V, VIH=3.5V, IO=1 A VIL =3.0V, VIH=7.0V, IO=1 A VIL =4.0V, VIH=11V, IO=1 A
V
IIN
Maximum Input Leakage Current
VIN= GND or VCC VIN= GND or VCC
uA uA
ICC Maximum Quiescent Supply Current (per Package) I Minimum Output Low (Sink) Current
VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V
mA
IOH
Minimum Output High (Source) Current
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IW4013B
AC Electrical Characteristics
(CL =50pF, RL =200 k , Input t r =t f =20 ns) VCC Guaranteed Limit V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 -55 C 3.5 8 12 300 130 90 300 130 90 400 170 120 200 100 80 25 C 3.5 8 12 300 130 90 300 130 90 400 170 120 200 100 80 7.5 125 C 3.0 6 10 450 200 150 450 200 150 600 250 150 250 150 100 Unit MHz
Symbol fmax
Parameter Maximum Clock Frequency (Figure 1)
tPLH, tPHL MaximumPropagation Delay, Clock to Q or Q (Figure 1) tPLH Maximum Propagation Delay, Set to Q or Q to (Figure 2)
ns
ns
Reset
tPHL
Maximum PropagationDelay,Set to QQ or Reset to (Figure 2) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance
ns
tTLH, tTHL
ns
CIN
pF
Timing Requirements
Symbol tw Parameter Minimum Pulse Width, Clock (Figure 1)
(CL =50pF, RL =200 kInput t r =t f =20 ns) , VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Guaranteed Limit -55 C 140 60 40 180 80 50 40 20 15 5 5 5 500 30 6 25 C 140 60 40 180 80 50 40 20 15 5 5 5 500 30 6 125 C 200 80 50 250 120 80 40 20 15 8 5 5 500 30 6 Unit ns
tw
Minimum Pulse Width, Set or Reset (Figure2)
ns
tsu
Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Maximum Input Rise or Fall Time, Clock (Figure 1)
ns
th
ns
tr, tf
s
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IW4013B
t CLOC
90 K 50% 10
tf r
tw VCC % 0V % SET O R RESET t PHL
%
VCC 0V VCC
%
tw 1/fma x tPL Q OR 90
50% 10%
t H
PHL
OR Q tPLH
50 Q
0V VCC
VCC % tTL OR 0 V Q t THL H
50%
0V
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
VCC
DAT
50% A
0V t su
CLOC
50% K
th
VCC
0V
Figure 3. Switching Waveforms
Expanded Logic Diagram (1/2 of the Device)
Address :
Postalcode:100039 Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Http://www.estek.com.cn Email:sales@estek.com.cn
6A06--6A07 Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
Fax : 010-58895793
REV No:01-060832
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